In addition to on-chip TriMatrix Memory structures, Stratix® series FPGAs feature I/O structures designed to allow the direct connection of high-performance external memories. Over time, Stratix series FPGAs have progressed from DDR SDRAM operating at 400 Mbps to DDR3 SDRAM operating at 1067 Mbps. A full listing and comparison of the supported memory interface types for all Altera® high-end FPGAs is available on Altera's External Memory Solutions Center.
Table 1 lists all the relevant resources and downloads needed to assist in the interfacing of Stratix series FPGAs to external memory devices.
| Table 1. Stratix Series External Memory Resources | ||
| Collateral | Description | Key (1) |
|---|---|---|
| Start Here | ||
| AN 435: Design Guidelines for Implementing DDR & DDR2 SDRAM Interfaces in Stratix III Devices (PDF) | Describes typical DDR and DDR2 SDRAM memory interface design flow for Stratix III FPGAs. Also provides links to pertinent literature for each design step. | A |
| AN436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices (PDF) | Describes typical DDR3 SDRAM memory interface design flow for Stratix III and Stratix IV FPGAs. Also provides links to pertinent literature for each design step. | A |
| AN 449: Design Guidelines for Implementing External Memory Interfaces in Stratix II and Stratix II GX Devices (PDF) | Describes typical memory interface design flow for Stratix II and Stratix II GX devices. Also provides links to pertinent literature for each design step. | A |
| Device Selection | ||
| Selecting the Right High-Speed Memory Technology for Your System (PDF) | Describes how to select the right memory for your application. | A/L |
| The Efficiency of the DDR & DDR2 SDRAM Controller Compiler (PDF) | Describes terminologies such as bandwidth, efficiency, and read latency. | A/L |
| External Memory Interfaces in Stratix III Devices (PDF) | Describes Stratix III device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers. | A |
| IP/Megafunction User Guides | ||
| DDR/DDR2 SDRAM High-Performance Controller User Guide (PDF) | Describes the controller interface and the design flow using the MegaWizard® Plug-In Manager and ALTMEMPHY. | A |
| ALTMEMPHY Megafunction User Guide (PDF) | Describes the ALTMEMPHY megafunction functionality and how to interface with Altera’s DDR and DDR2 SDRAM high-performance controllers and third-party controllers. | A |
| IP MegaStoreTM Web Page | Web page linking to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP of your interest. | A/L |
| Timing Analysis | ||
| AN 438: Constraining & Analyzing Timing for External Memory Interfaces in Stratix III Devices (PDF) | Describes the various timing related paths, constraints, and analysis used by the ALTMEMPHY megafunction in Stratix III designs. | A |
| TimeQuest Timing Analyzer (PDF) | Describes the features of the TimeQuest timing analyzer and how to constrain your design with SDC commands. | A/L |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | A/L |
| Models and Board Design Guidelines | ||
| AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines (PDF) | Describes the design guidelines for developing a dual DIMM DDR2 SDRAM memory interface. | A/L |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera devices. | A/L |
| HSPICE Models | Web page listing of all the HSPICE models for Altera devices. | A/L |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | A/L |
- A = New auto-PHY solution delivered via the ALTMEMPHY megafunction
L = Legacy core. DDR and DDR2 SDRAM Controller MegaCore® function
(integrated static datapath and controller solution)
