TriMatrix Memory in Stratix Series FPGAs

The TriMatrix on-chip memory used in today's high-performance Stratix^® series FPGAs offers maximum efficiency and flexibility and is based upon the TriMatrix memory architecture introduced with Altera's first Stratix device. Since its introduction, the implementation of TriMatrix memory has been optimized with each new Stratix series FPGA family as shown in table 1.

Table 1. TriMatrix Memory Blocks in Stratix Series FPGAs
Stratix Series FPGA Family	M512 512 Bits/Block	MLAB 640 Bits/Block	M4K 4096 Bits/Block	M9K 9,216 Bits/Block	M144K 147,456 Bits/Block	M-RAM 524,288 Bits/Block	Total MBits
Stratix IV		12,600		1,529	64		31,592,448
Stratix III		6,760		1,144	48		21,947,392
Stratix II	930		768			9	8,340,480
Stratix	767		364			9	6,602,240

Maximum FPGA Memory Efficiency and Bandwidth

By offering three different memory block sizes, Stratix series FPGAs allow you to select the best fit for your applications. TriMatrix memory significantly improves memory utilization and reduces the need for memory cascading. The MLAB and M9K blocks allow Stratix IV FPGAs to offer more data ports or memory bandwidth than other FPGAs. Table 2 shows how you can use TriMatrix memory to address a variety of memory applications.

Memory Block	Applications
*Table 2. TriMatrix Memory Application Examples*
M512 / MLAB	Shift registers Small FIFO buffers Filter delay lines
M4K / M9K	General-purpose memory Packet header or cell buffers
M144K / M-RAM	Processor code storage Packet buffers Video frame buffers

TriMatrix Memory in Stratix Series FPGAs

Maximum FPGA Memory Efficiency and Bandwidth

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