Verification and Board-Level Tools

• ASIC-strength timing analysis tool
• Native support for industry-standard Synopsys Design Constraint (SDC) format
• Support for complex clocking schemes
• Improved performance
• Easier ASIC prototyping
• Easy to use GUI

      View Video     Training      Support     Handbook (PDF)

• Automatically routes high-performance paths and then programs the non-performance paths as low power
• Programmable Power Technology
• Automatically powers down unused logic
• Dramatically reduces overall power use

      View Video     Training      Support     Handbook (PDF)

• Helps you achieve timing closure faster and shorten verification time
• Provides analysis and editing capabilities in an integrated floorplan
• Allows you to make floorplan assignments, implement engineering change orders (ECOs), and perform power analysis

      Training     Support     Handbook (PDF)

• A system-level debugging tool that captures and displays real-time signal behavior
• Gives you the ability to observe interactions between hardware and software in system designs
• Supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer
• Gives you enhanced control over data sampling and display
• Graphical interface

      Training     Support     Handbook (PDF)

• Provides powerful ways to view your initial and fully mapped synthesis results during the debugging optimization, or constraint entry process
• Allows you to view your initial synthesis results to determine whether you have created the desired logic

      View Video     Training      Support      Handbook (PDF)

• Integrated seamlessly with the Quartus II Pin Planner to interactively manage pin assignments
• Provides feedback on potential simultaneous switching noise (SSN) violations during pin assignments
• You can interactively manage pin assignments, reduce SSN violations allowing for faster board design, and shorten system-level debug time
• Only currently available for the Stratix^® III FPGA family