Stratix/Stratix GX Device Configuration

Configuration scheme overview

Stratix^®/Stratix GX devices support the following configuration schemes:

• Serial—Used to conserve pins
  • Passive Serial (PS)
    • Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device, or a microprocessor to control the configuration process synchronously and supply the configuration data serially to a Stratix/Stratix GX device.
  • JTAG
    • Configures Stratix/Stratix GX devices via the IEEE Standard 1149.1 interface.
• Parallel—Used for faster configuration
  • Fast Passive Parallel (FPP)
    • Uses an external intelligent host, such as a PC, an EPC device, or a microprocessor to control the configuration process synchronously and supply the configuration data in a parallel manner to the Stratix/Stratix GX device.
  • Passive Parallel Asynchronous (PPA)
    • Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process asynchronously and supply the configuration data in a parallel manner to the Stratix/Stratix GX device.

How to configure Stratix/Stratix GX devices

• For prototyping or debugging
  • Using Altera Programming Cables
    • The Quartus^® II programmer supports configuring Stratix/Stratix GX devices directly using PS or JTAG interfaces via Altera^® programming cables.
• In the field
  • Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet (PDF)
    • The EPC device configures the Stratix/Stratix GX device automatically after power up. However, you need to program the EPC device first.
  • MAX Series Configuration Controller Using Flash Memory white paper (PDF) 
    • A MAX^® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs.
    • Source code (ZIP)

Frequently asked questions

1. What is the configuration file size of EP1S10 ES devices?
2. What solutions does Altera offer for soft-error/SEU mitigation?
3. Which of the Altera devices support CONFIG_IO instruction?
4. Do I need a pull-up resistor on the DATA configuration input signal of my Stratix, Stratix GX, or Cyclone^® device?
5. Does JRunner support Stratix 1S10 engineering sample (ES) devices?
6. Does the static supply current for Stratix, Stratix GX, and Cyclone devices differ before and after configuration?
7. Does Quartus II software version 3.0 support remote system configuration in Stratix and Stratix GX devices?
8. Why doesn't the AnF bit of the control register in the remote configuration block set to "1" when the Stratix or Stratix II device is configured with the application image?
9. What is CONFIG_IO?
10. Why does the configuration behavior for an Altera FPGA behave differently with Quartus II software versions 4.1 and 4.2 if there is a configuration device that performs configuration if nCONFIG is toggled?